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24AA515/24LC515/24FC515
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS
Industrial (I):
V CC = +1.7V to 5.5V T A = -40°C to +85°C
Param.
No.
1
Sym.
F CLK
Characteristic
Clock frequency
Min.
—
Max.
100
Units
kHz
Conditions
1.7V ≤ V CC ≤ 2.5V
—
—
400
1000
2.5V ≤ V CC ≤ 5.5V
2.5V ≤ V CC ≤ 5.5V (24FC515 only)
2
T HIGH
Clock high time
4000
—
ns
1.7V ≤ V CC ≤ 2.5V
600
500
—
—
2.5V ≤ V CC ≤ 5.5V
2.5V ≤ V CC ≤ 5.5V (24FC515 only)
3
T LOW
Clock low time
4700
—
ns
1.7V ≤ V CC ≤ 2.5V
1300
500
—
—
2.5V ≤ V CC ≤ 5.5V
2.5V ≤ V CC ≤ 5.5V (24FC515 only)
4
T R
SDA and SCL rise time
—
1000
ns
1.7V ≤ V CC ≤ 2.5V
(Note 1)
—
—
300
300
2.5V ≤ V CC ≤ 5.5V
2.5V ≤ V CC ≤ 5.5V (24FC515 only)
5
T F
SDA and SCL fall time
—
300
ns
All except, 24FC515
(Note 1)
—
100
2.5V ≤ V CC ≤ 5.5V (24FC515 only)
6
T HD : STA Start condition hold time
4000
—
ns
1.7V ≤ V CC ≤ 2.5V
600
250
—
—
2.5V ≤ V CC ≤ 5.5V
2.5V ≤ V CC ≤ 5.5V (24FC515 only)
7
T SU : STA
Start condition setup time
4700
—
ns
1.7V ≤ V CC ≤ 2.5V
600
250
—
—
2.5V ≤ V CC ≤ 5.5V
2.5V ≤ V CC ≤ 5.5V (24FC515 only)
8
T HD : DAT Data input hold time
0
—
ns
(Note 2)
9
T SU : DAT
Data input setup time
250
—
ns
1.7V ≤ V CC ≤ 2.5V
100
100
—
—
2.5V ≤ V CC ≤ 5.5V
2.5V ≤ V CC ≤ 5.5V (24FC515 only)
10
T SU : STO Stop condition setup time
4000
—
ns
1.7V ≤ V CC ≤ 2.5V
600
250
—
—
2.5V ≤ V CC ≤ 5.5V
2.5V ≤ V CC ≤ 5.5V (24FC515 only)
11
T SU : WP
WP setup time
4000
—
ns
1.7V ≤ V CC ≤ 2.5V
600
600
—
—
2.5V ≤ V CC ≤ 5.5V
2.5V ≤ V CC ≤ 5.5V (24FC515 only)
12
T HD : WP
WP hold time
4700
—
ns
1.7V ≤ V CC ≤ 2.5V
1300
1300
—
—
2.5V ≤ V CC ≤ 5.5V
2.5V ≤ V CC ≤ 5.5V (24FC515 only)
13
T AA
Output valid from clock
—
3500
ns
1.7V ≤ V CC ≤ 2.5V
(Note 2)
—
—
900
400
2.5V ≤ V CC ≤ 5.5V
2.5V ≤ V CC ≤ 5.5V (24FC515 only)
14
T BUF
Bus free time: Time the bus
4700
—
ns
1.7V ≤ V CC ≤ 2.5V
must be free before a new
transmission can start
1300
500
—
—
2.5V ≤ V CC ≤ 5.5V
2.5V ≤ V CC ≤ 5.5V (24FC515 only)
15
T OF
Output fall time from V IH
10 + 0.1C B
250
ns
All except, 24FC515 (Note 1)
minimum to V IL maximum
C B ≤ 100 pF
250
24FC515 (Note 1)
16
T SP
Input filter spike suppression
—
50
ns
All except, 24FC515 (Notes 1 and 3)
(SDA and SCL pins)
17
T WC
Write cycle time (byte or page)
—
5
ms
18
Endurance
1M
—
cycles
25°C (Note 4)
Note 1:
2:
3:
4:
Not 100% tested. C B = total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
The combined T SP and V HYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike
suppression. This eliminates the need for a TI specification for standard operation.
This parameter is not tested but established by characterization. For endurance estimates in a specific application,
please consult the Total Endurance? Model which can be obtained from Microchip’s web site at www.microchip.com.
? 2008 Microchip Technology Inc.
DS21673G-page 3
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